The MOS-AK Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual Q4 event on December 7, 2016 UC Berkeley as its 9th consecutive International MOS-AK Workshop. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was hosted by Prof. Jaijeet Roychowdhury of EECS at the University of California at Berkeley and co-sponsored by Keysight Technologies and NEEDS.
This hands-on workshop will focus on the newly developed Verilog-A to ModSpec device model translator for MAPP, dubbed VAPP (Verilog-A Parser and Processor). The goal of the workshop is to illustrate how VAPP/MAPP facilitates the development of simulation ready compact models. An overview of MAPP's multi-physics modelling and simulation capabilities will also be provided. A hands-on refresher on MAPP will be provided for those who have no prior experience with it.
Variability has emerged as a fundamental challenge to IC design in scaled CMOS technology; and it has profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled via improvements in the manufacturing process, comprehensive methods are necessary to assess and manage the negative effects of variability, which in turn requires accurate and tractable variability models. The goal of the VMC workshop is to provide a forum for theoreticians and practitioners to freely exchange opinions on current practices as well as future research needs in variability modeling and characterization. The 2015 VMC was co-organized with NSF-SRC NEEDS.
Annual summer schools address nanoelectronics from science to circuits and systems. (2015 Summer School on Uncertainty Quantification is now available.)
This workshop is designed to help attendees get started using MAPP in a hands-on manner. Attendees will learn how to write and test models in MAPP, how to translate them to Verilog-A, and how to use MAPP to validate Verilog-A models.
This workshop presented a tutorial introduction to the Matlab-based compact model development platform being developed at UC Berkeley.
Compact models must get the physics right, work reliably over bias, geometry, and temperature, interact properly with the circuit simulators in which they are implemented, run efficiently, and follow impeccable software development practices. This workshop will be a detailed deep-dive into an industrial strength Verilog-A code for the R3 model for JFETs, diffused resistors, and polysilicon resistors. Do not think that a “resistor” is a trivially simple device to model: real resistors are affected by depletion pinching, velocity saturation, and self-heating, and to properly account for all of these effects, while ensuring no unphysical model behavior, is not trivial. But it is not as complex as a complete MOS or bipolar transistor model – so is ideal as a training vehicle for compact modeling.
Mini-Workshop on Carbon-Nanotube FETs